[FIXED] What will happen on dcache in backends when one physical address mapped different virtual address?

Issue

im puzzled on cache issue for arm. Here, I mapped the same block or physical memory and got two different virtual address without O_SYNC, that's both two would be cached: (assume I only access the first 4 bytes of the two)

1. If i read two address, how many dcache entries would be loaded, one or two?
2. If i did write operation on one virtual memory, how many dcache entries would be marked dirty, one or two(if have to dcache entries)? what happened at the backends for dcache entries?

Thanks.

Solution

Recent ARMs are specified to behave as if the caches are physically tagged (e.g. cache lines identified by physical addresses), so multiple aliased virtual addresses (even in separate processes) should reflect the same physical cache line.

This isn't universally true; older ARM cores prior to the ARM-v7A architecture supported virtually tagged caches.

Answered By - solidpixel

Answer Checked By - David Goodson (PHPFixing Volunteer)